JEDEC STANDARD Board Level Drop Test Method of Components for Handheld Electronic Products JESDB JULY JEDEC SOLID. The reliability of this package has been studied by employing the JEDEC JESDB standard drop test. In this paper, the JEDEC B-condition is applied to. The need for RoHS compliant boards coupled with the demand for reliable electronics has resulted in the development of the JEDEC Standard JESD B to.
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The board shall have matching daisy chain pattern such that one or multiple nets are formed through all interconnects after component mounting.
JEDEC standards and publications are designed to serve the public interest through eliminating misunderstandings between manufacturers and purchasers, facilitating interchangeability and improvement of products, and assisting the purchaser in selecting and obtaining with minimum delay the proper product for use by those other than JEDEC members, whether the standard is to be used either domestically or internationally.
Data analysis showing mean and standard deviation of failure data according to component groupings. The use of shoulder screw eliminates jeds22 need to re-tighten screws between drops. The test data generated using such a board shall be correlated at least once by generating the same data on same component using the preferred board defined in this document.
Test data suggests that the variations in response acceleration and strain are reduced significantly if this screw is used. The information included in JEDEC standards and publications represents a sound approach to product specification and application, principally from the solid state device manufacturer viewpoint.
I recommend changes to the following: All components used for this testing must be daisy-chained. Since components with body sizes larger than 15 mm x 15 mm in size are not used in these applications, the maximum size of the component body covered in this standard is 15 mm x 15 mm. Requirement, clause number Test method number Clause number The referenced clause number has proven to be: Because of symmetric component design and support locations, grouping see Table 6 can be used for data analysis for boards mounted with 15 components refer Figure 1.
A packaged semiconductor device. Depending on the monitoring system used, the failure is defined as follows: Component length and width. It is recommended that the component mounting pads on the PCB be designed as per the specification in Table 3 for area array devices. Therefore, options are provided for mounting just 1 or 5 components on the board using the following locations: A visual inspection shall be performed on all boards for solder mask registration, contamination, and daisy chain connection.
BOARD LEVEL DROP TEST METHOD OF COMPONENTS FOR HANDHELD ELECTRONIC PRODUCTS | JEDEC
Additional strain gages may also be mounted at different locations on the board to fully characterize the strain response of the assembly.
Jesc22 of Thermal Agin It should be noted that the peak acceleration and the pulse duration is a function b11 not only the drop height but also the strike surface. This test method is not meant to address the drop test methods required to simulate shipping and handling related shock of electronic subassemblies.
The bottom of the drop table is usually rounded slightly to ensure very small area of contact with the strike surface. The locations of these holes are shown in Figure 1.
Means shall be provided in the apparatus such as automatic braking mechanism to eliminate bounce and to prevent multiple shocks to the board.
Although it is recommended that this characterization be performed for previously untested components, this may not be required if such characterization data is available for v111 sized component.
JESDB B Board level drop test menthod of components for handheld eletronic products_百度文库
The composite values Modulus, and Tg shall be measured on at least one representative test board at component mounting location. All routing and traces within and just outside the component footprint shall be done on layer 2 and layer 8 for area array packages and layer 1 and layer 8 for perimeter leaded packages.
Similarly, a larger group containing components in Group B and D may also exist. The fundamental mode results in maximum displacements and is typically most damaging. Table 1 h111 the thickness, copper coverage, and the material for each layer. During the test, the shock pulse shall be measured for each drop to ensure that input pulse remains within the specified tolerance.
The area of the board in the length direction outside of components shall be restricted for labeling, through holes, edge fingers, and any other fixtures, if needed. Therefore, it is recommended that this characterization should only be done on a set-up board. Wherever necessary, additional test points within each net shall b111 incorporated for failure location identification. All cables shall be cleared from the drop path.
The number of washers used shall be the same for all four screws. Smaller clearance can be used as long as it does not cause any solder mask encroachment on pads due to misregistration.
Publications Department Wilson Blvd. In the event that shock condition in addition to the required Condition B is used to conduct the test, the maximum number of drops shall be determined using the acceleration factor between the two conditions for similar sized components. This is pictorially shown in Figure 3. Experience with different board iesd22 has suggested that the horizontal board orientation with components facing down results in maximum PCB flexure and, thus, the worst orientation for failures.
An electrical discontinuity of resistance greater than ohms lasting for 1 microsecond or longer.
BOARD LEVEL DROP TEST METHOD OF COMPONENTS FOR HANDHELD ELECTRONIC PRODUCTS
For board Side A, the microvias in pads shall be created with laser ablation with via diameter of microns. Board thickness, warpage, and pad sizes shall also be measured using a sampling plan.
A visible partial separation of component from the test board, even without a significant increase in resistance or intermittent discontinuity, shall also be considered as a failure. In addition, a rectangular rosette strain gage shall be mounted on this set-up board nesd22 position U8 on the other side non-component side of the board to characterize g111 in x and y directions as well as the principal strain and principal strain angle.
The additional data shall directly compare the effect of optional component mounting 1 or 5 components to the preferred component mounting configuration. The electrical resistance of each net shall be measured in-situ during each drop and all failures shall be logged. Other suggestions for document improvement: This is the applied shock pulse to the base plate and shall be measured by accelerometer mounted at the center of base plate or close to the support posts for the board.
This dropping event can not only cause mechanical failures in the housing of the iesd22 but also create electrical failures in the printed circuit board PCB assemblies mounted b11 the housing due to transfer of energy through PCB supports. As wires soldered to the board for electrical continuity test may also come off during the test, it is highly recommended that all electrical connections be checked once jsed22 failure in indicated to ensure that the failure is due to component to board interconnection failure.
There shall be four holes on the board to be used for mounting board on drop test fixture.